By Dimitris Gizopoulos
This is a brand new form of edited quantity within the Frontiers in digital trying out publication sequence dedicated to fresh advances in digital circuits trying out. The ebook is a complete elaboration on very important themes which seize significant study and improvement efforts this present day. "Hot" subject matters of present curiosity to check expertise neighborhood were chosen, and the authors are key members within the corresponding topics.
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Additional resources for Advances in Electronic Testing: Challenges and Methodologies (Frontiers in Electronic Testing)
Again, these results were used to justify multiple, sometimes conflicting, actions. At HP, they spurred the effort that eventually lead to the current ratios technique, while for others they showed that IDDQ was a wasteful test that should be removed from production. At-speed functional IDDQ 731 1 At-speed functional IDDQ 140 7 0 Stuck-at scan 5 179 3 17 3 7 0 0 0 1 0 22 20 0 AC scan Plus 4 = fail only IDDQ + AC scan Stuck-at scan 2 175 3 21 3 25 22 AC scan Plus 2 = fail only IDDQ + AC scan Figure 1-28: Effectiveness of IDDQ versus other tests  (left diagram for 50uA, right diagram for 200uA).
6 27 IDDQ Models In addition to conventional logic testing, where inputs are applied to a circuit and output responses are measured, circuits can be tested parametrically. One example of such a test is an IDDQ test (IDD is the drain current in a CMOS circuit, the “Q” refers to the quiescent or static state). In an IDDQ test, a set of inputs is applied, then the circuit is allowed to settle and the current flowing through the power supply is measured. A circuit that draws more current than some threshold value is identified as defective.
This section describes the required elements of such a strategy; that is, a comprehensive approach to chip testing beginning with a defect analysis and comprising multiple test types or methods. 1 Logic Tests Logic testing, most typically using scan vectors, remains the most common and useful technique for quickly identifying bad parts. The vast majority of these tests are developed using the single stuck-at fault model, and most commercial ATPG tools are based on it. Since few defects manifest themselves as single stuck-at 12 faults , what should be done for logic testing in a Defect-Oriented test 13 strategy ?